The present invention relates to semiconductor device manufacturing methods. More particularly, the invention relates to a semiconductor device manufacturing method which includes a step of depositing electrode metal selectively by the utilization of two adjacent walls formed on a semiconductor substrate.
A Schottky barrier gate field-effect transistor (hereinafter referred to as a "MES FET" when applicable) employs a Schottky barrier for its gate electrode which is formed by depositing metal in contact with a semiconductor surface. MES FETs are extensively employed in low-noise amplifiers, high-output amplifiers or oscillators in the range of microwave frequencies.
FIGS. 1A-1D show the manufacturing steps used in a conventional MES FET manufacturing method. As shown in FIG. 1A, an active layer 2 is formed on a semi-insulating semiconductor wafer 1 by epitaxial growth. The region of the active layer 2 is limited to a desired extent by mesa etching as seen in FIG. 1B. In FIG. 1C, a source electrode 3 and a drain electrode 4 are formed with Au-Ge-Ni alloy using ordinary vacuum evaporation and lithography techniques and thereafter the wafer is subjected to heat treatment at about 470.degree. C. for several minutes. Then, a gate electrode 5 is formed in a region of the active layer 2 between the source electrode 3 and the drain electrode 4 using ordinary vacuum evaporation and lithography techniques.
In order to improve the high frequency response of a MES FET, it is necessary to make the gate length l as short as possible. Accordingly, the element must be manufactured with considerably high precision. In the conventional manufacturing method described above, in the formation of the pattern of the gate electrode 5 using photoresist material (hereinafter termed simply "resist"), steps are formed in the vicinity of the gate pattern by the source electrode 3 and the drain electrode 4. Accordingly, the resolution of the gate pattern is not so good as in the case that the patterns were formed on a flat surface. Thus, it is difficult to form a gate pattern as short as 1 .mu.m with the conventional manufacturing method. In addition, while it is necessary to form the gate electrode with a high alignment accuracy on the order of .+-.0.2 .mu.m between the source electrode 3 and the drain electrode 4 which were previously formed, it is considerably difficult using known techniques to locate these electrodes with such a high accuracy. Accordingly, the conventional manufacturing method provides a very low manufacturing yield.
Usually in the manufacture of devices of this type, a method is employed in which, prior to the formation of the gate electrode 5, the source electrode 3 and the drain electrode 4 are subjected to an alloying treatment to reduce the contact resistances thereto. However, if the heat treatment is carried out at a sufficiently high temperature for a long time, metal cohesion or balling-up occurs in the source and drain electrodes, which increases the magnitudes of the steps therearound. This is one of the factors which adversely affects the resolution of the gate photoresist pattern.
Accordingly, an object of the invention is to eliminate the above-described drawbacks accompanying a conventional semiconductor device manufacturing method. More specifically, an object of the invention is to manufacture short-gate MES FETs with a high yield.